Ca3140 Unit 4 Ap

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CA3140, CA3140A
Data Sheet February 10, 2005 FN957.9

4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output
The CA3140A and CA3140 are integrated circuit operational amplifiers that combine the advantages of high voltage PMOS transistors with high voltage bipolar transistors on a single monolithic chip. The CA3140A and CA3140 BiMOS operational amplifiers feature gate protected MOSFET (PMOS) transistors in the input circuit to provide very high input impedance, very low input current, and high speed performance. The CA3140A and CA3140 operate at supply voltage from 4V to 36V (either single or dual supply). These operational amplifiers are internally phase compensated to achieve stable operation in unity gain follower …show more content…
Output Resistance Equivalent Wideband Input Noise Voltage (See Figure 27) Equivalent Input Noise Voltage (See Figure 35)

RI CI RO eN eN BW = 140kHz, RS = 1MΩ RS = 100Ω f = 1kHz f = 10kHz

1.5 4 60 48 40 12 40 18 4.5 9 220

1.5 4 60 48 40 12 40 18 4.5 9 220 0.08 10 4.5 1.4

TΩ pF Ω µV nV/√Hz nV/√Hz mA mA MHz V/µs µA µs % µs µs

Short Circuit Current to Opposite Supply

IOM+ IOM-

Source Sink

Gain-Bandwidth Product, (See Figures 6, 30) Slew Rate, (See Figure 31) Sink Current From Terminal 8 To Terminal 4 to Swing Output Low Transient Response (See Figure 28)

fT SR

tr OS

RL = 2kΩ CL = 100pF RL = 2kΩ CL = 100pF Voltage Follower

Rise Time Overshoot To 1mV To 10mV

0.08 10 4.5 1.4

Settling Time at 10VP-P, (See Figure 5)

tS

Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Large Signal Voltage Gain (Note 3) (See Figures 6, 29)

For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified CA3140 SYMBOL |VIO| |IIO| II AOL MIN 20 86 TYP 5 0.5 10 100 100 MAX 15 30 50 MIN 20 86 CA3140A TYP 2 0.5 10 100 100 MAX 5 20 40 UNITS mV pA pA kV/V dB

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FN957.9 February 10, 2005

CA3140, CA3140A
Electrical Specifications
PARAMETER Common Mode Rejection Ratio (See Figure 34) Common Mode Input Voltage Range (See Figure 8) Power-Supply Rejection Ratio, ∆VIO/∆VS (See Figure 36) Max Output Voltage (Note 4) (See Figures 2, 8) Supply Current (See Figure 32) Device Dissipation Input Offset

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