4DM4 Course Essay example

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“A Brief Introduction to VHDL”
Tuesday, Thursday - Sept 9, 11, 2014

Prof. Ted Szymanski
Dept. of ECE
McMaster University

4DM4 VHDL-tutorial, 2014, Page

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(c) Prof. Ted Szymanski

5 Classes of VHDL statements
•! A VHDL design includes 5 types of statements
•! LIBRARY ; a file which includes predefined hardware component declarations, provided by Altera, IEEE, etc
•! PACKAGE ; a file which includes shared data type definitions in one file
•! ENTITY ; specifies a logic block with its exact I/O ports
•! ARCHITECTURE ; (a) specifies what an entity does (a ‘behavioural’ description) or (b) what an entity is composed of (a ‘structural’ description) or (c ) specifies a combined behavioral & structural descriptions (a ‘dataflow’ description)
•! CONFIGURATION ; statement which specifies which versions of entities to use; a version control system
•! These classes of statements can be in the same file, or separate files which can be compiled separately, but the order must be preserved for the compiler. 4DM4 VHDL-tutorial, 2014, Page

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(c) Prof. Ted Szymanski

IEEE Libraries and Packages
•! The library “ieee” contains several packages of definitions standardized by IEEE, which can be used in all IEEE-certified VHDL environments;
•! We’ll always use the ieee definitions
!Library!

Package! !

!
!
!

ieee! ! ieee! ! ieee! !

std_logic_1164! ! std_logic_arith! ! std_logic_signed! !

!
!

ieee! !
STD!!

std_logic_unsigned! unsigned numbers only
STANDARD! ! very basic types (ie BIT)

!

STD!!

TEXTIO! !

4DM4 VHDL-tutorial, 2014, Page

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Contents standard data types (bit, byte..) signed and unsigned numbers, converters signed numbers only

definitions for user I/O, printing messages

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(c) Prof. Ted Szymanski

Defining the Signal Types
(IEEE’s Std_logic_1164 Package)
•! The type std_ulogic consists of 9 symbolic values;
TYPE std_ulogic IS ( ! ‘U’, -- Uninitialized
! !! ! ‘X’, -- Forcing Unknown
! !! ! ‘0’, -- Forcing 0
! !! ! ‘1’, -- Forcing 1
! !! ! ‘Z’, -- High impedance
! !! ! ‘W’, -- Weak unknown
! !! ! ‘L’, -- Weak 0
! !! ! ‘H’, -- Weak 1
! !! ! ‘-’, -- Don’t care );
•! The type “std_logic” uses the same 9 values, after resolution (when multiple values are driven onto a wire, one value “wins” )
•! Std_logic allows modelling of 3-state logic, weak signals, etc

4DM4 VHDL-tutorial, 2014, Page

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(c) Prof. Ted Szymanski

Type Converters between Signal Types
•! BIT_VECTOR is different from STD_LOGIC_VECTOR
•! SIGNED is different from UNSIGNED
•! UNSIGNED’(“1010”) represents +10
•! SIGNED’(“1010”) represents -6
•! library “ieee”, package “ieee.std_logic_arith”, provides several built-in type converter functions:
•! CONV_INTEGER (signal/variable, #bits)
•! CONV_UNSIGNED (signal/variable, #bits)
•! CONV_SIGNED (signal/variable, #bits)
•! CONV_STD_LOGIC_VECTOR (signal/variable, #bits)
•! (The parameter “#bits” can be optional)

4DM4 VHDL-tutorial, 2014, Page

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(c) Prof. Ted Szymanski

Entities & Architectures
•! Entity = hardware module with a unique name
•! Entity…