Essay on ECE 3561 Lecture 12 VHDL Overview

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L9 – VHDL Overview

VHDL Overview



Rules for State Assignment
Application of rule
Gate Implementation



Ref: text Unit 15.8




9/2/2012 – ECE 3561 Lect
9

Copyright 2012 - Joanne DeGroat, ECE, OSU

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Overview


HDL – Hardware Description Language






A language that allows description of hardware for documentation, simulation, synthesis, verification, …

To use an HDL you need a CAD system that supports it.
Major CAD systems support VHDL, Verilog, System C,
System Verilog
CAD systems (just some of them)





Cadence – Incisive
Mentor Graphics (Model Sim) – ModelSim, Questa
Altera, XILINX
Synopsis – Mainly toward synthesis and ASIC production from
HDL descriptions

1/8/2007 - L2 VHDL
Introcution

© Copyright 2012 - Joanne DeGroat, ECE, OSU

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A brief history of HDLs


The development of today’s HDL began in
1980.







State of CAD – generators and proprietary HDLs
VHDL requirements set in 1981
VHDL IEEE 1st standard in 1987 – New versions in 1993, 1997, 2000, 2002, 2008. And a new version is being worked on.

Verilog 1st standard was in 1995
System C 1st standard was in 2005

9/2/2012 – ECE 3561 Lect
9

Copyright 2012 - Joanne DeGroat, ECE, OSU

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Common to all systems





Have source HDL file
Structure of generated files is common
Source Files
Library files are for design units

Analysis
(Compile)

Simulation

1/8/2007 - L2 VHDL
Introcution

© Copyright 2012 - Joanne DeGroat, ECE, OSU

VHDL
Library Files

Synthesis

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A First Example






Desire to do a VHDL description of a full adder.
A device consists of


An Interface



An operational part

Interface – The INPUTS AND OUTPUTS
Operational Part – The FUNCTIONAL
BEHAVIOR

1/8/2007 - L2 VHDL
Introcution

© Copyright 2012 - Joanne DeGroat, ECE, OSU

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VHDL Entity Design Unit


Format






For a full adder would have:








ENTITY unit_name IS
[port_clause]
END unit_name;

ENTITY full_adder IS
PORT(a,b,cin : IN bit; sum : OUT bit; cout : OUT bit);
END full_adder;

The PORT portion is termed a Port Clause


When specified in the port clause these signals have scope over all architectures of this entity

1/8/2007 - L2 VHDL
Introcution

© Copyright 2012 - Joanne DeGroat, ECE, OSU

7

Signals/Port Modes/Types



PORT(a,b,cin:IN bit; sum:OUT bit; cout: OUT bit);
Signals: Names referenced in the Port Clause are signals. 




A,b,cin,sum,cout represent wires of the physical unit.
SIGNALS are objects that have both a value and a time component. Port Modes: In this example you have inputs and outputs. The Port Mode specifies the direction of the signal transfer and a couple of other properties of the port. 1/8/2007 - L2 VHDL
Introcution

© Copyright 2012 - Joanne DeGroat, ECE, OSU

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Signals/Port Modes/Types


Modes:








IN – signal can only be used (i.e., can only be read or can only be used on the right-hand-side of an equation).
CANNOT BE ASSIGNED TO!!
OUT – signal value can only be written. Cannot be seen or used in the design as it is an output and therefore external. INOUT – signal can be both written to (assigned to) and read (used). However, signals of thie type are connected to busses and therefore this signal mode requires the signal to be resolved.
BUFFER – signal value can be written to and used internally in the design.

1/8/2007 - L2 VHDL
Introcution

© Copyright 2012 - Joanne DeGroat, ECE, OSU

9

Basic Types



Built in – part of the standard and the language proper.
TYPE BIT – your typical binary type with values of
‘0’ and ‘1’.


Declaration that established this type








TYPE BIT is (‘0’, ‘1’);

Use of SIGNALS of TYPE bit a <= ‘0’; b <= x AND y OR z;

Note that the value is either ‘0’ or ‘1’

1/8/2007 - L2 VHDL
Introcution

© Copyright 2012 - Joanne DeGroat, ECE, OSU

10

Architectural Design Unit


Specifies the operational part








ARCHITECTURE identifier OF entity_id IS
[declarations]
BEGIN
[architecture_statement_part]
END [identifier];…