Research Paper On Thyristor

Words: 1630
Pages: 7

Muktesh Waghmare, Raman Gaikwad

1: Principle:
Thyristor is well-known for its high-current drive capability and its bi-stable characteristics. It has been widely used in power electronics applications. With the exponential advances in CMOS technology tiny thyristor devices can now be easily embedded into conventional nano-scale CMOS. This enables the creation of a memory cell technology with features that include small cell size, high performance, reliable device operation, and good scalability. Use of thyristor provides a positive regenerative feedback that results in very large bit cell operation margins. The difference is that the four-transistor CMOS latch of a 6T-SRAM is replaced by the PNP-NPN bipolar latch of a
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A large current will indicate logic ‘1’ and vice versa. During the stand-by ‘ON’ state the holding current to the thyristor is provided by the sub-threshold current of the access transistor
Simplified diagram and waveforms:

3.2: Thyristor based D-RAM:

CONCEPT: The new TCCT DRAM memory cell is constructed using three control lines; bit line, word line, and write enable line. The anode node is connected to a bit line (anode line) and the cathode node is connected to a word line (cathode line). The gate poly line itself functions as a write enable line. [4] For write 1, gate line is pulsed while cathode line is held at ground level, triggering the TCCT device to latch. The bias scheme for write zero operation is the same as write one except that bit line voltage is kept low (Vwrite0) so that the pulsing of the gate line switches the TCCT into its blocking state. For Read operation, the cathode line is held low and the change in the voltage or the current of the bit-line is read into a sense amplifier. The write enable line at the gate is not active in read operation.In standby mode, both anode and cathode lines are at Vdd and the stored cell data is maintained by the charge state of the P-base of TCCT.


4: Typical cell characteristics:
4.1: Thyristor S-RAM:
Cell area: 0.56µm2 (130 nm SOI technology)
Read operation: <1.7 ns
Write operation: <2